1. Technical Field of the Invention
This invention relates generally to mixed signal circuitry and more particularly to clock generating circuitry.
2. Description of Related Art
As is known, a clock circuit generates a clock signal for one or more circuit blocks (e.g., processing core, memory, interfaces, etc.) within an integrated circuit (IC). Typically, an IC will include a plurality of circuit blocks, wherein at least some of the circuit blocks require a different clock signal than other circuit blocks. Depending on the difference between the clock signals, a single clock circuit may generate the needed clock signals. For example, when one circuit block requires a 10 MHz clock signal and another circuit block requires a 5 MHz clock signal, a single clock circuit may generate the 10 MHz clock signal and further include a frequency divider circuit to produce the 5 MHz clock.
As another example, when a first circuit block requires a 480 MHz clock, a second circuit block requires a 350 MHz clock, a third circuit block requires a 133 MHz clock, and a fourth circuit block requires a 54 MHz clock, multiple clock circuits are used to generate the need clock signals. Typically, a phase locked loop (PLL) is the primary component of a clock circuit. When an integrated circuit includes multiple PLLs there is a likelihood of noise and/or timing issues between the circuit blocks. In addition, multiple clock circuits increase the size of the die area, consume a significant amount of power, and require off chip crystal oscillators, thereby increasing the cost of a device incorporating the IC.
Therefore, a need exists for a single clock circuit that produces multiple clock signals having a variety of clock rates.